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| VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 Features * High-Speed Operation: 1 Gb/s Data Rate 500ps min Output Pulse Width 750ps min Input Pulse Width * Excellent Overall Timing Accuracy: Ultra-Stable Timing Delays Minimum Pattern Dependence Very Fine Timing Resolution (1 LSB = 8ps) * High Level of Integration Reduces Board Area: 16 Independently Adjustable Delay Lines in a Single Package * Configurable as 2 1:8 or 1:16 1Gb/s 16-Channel Drive-Side Deskew IC * Wide Span: > 4ns Usable Range * Pulse Width Adjustment to Compensate for Dispersion in Pin Electronics: 2ns Independent Adjustment of Rising and Falling Edges * Fully Digital Single-Chip Solution: No Off-Chip DACs Required No DAC-Induced Timing Errors from Analog Crosstalk, Reference Noise, Temperature, or Voltage Drift * Single Power Supply: -2V @ 5W * 128-Pin PQFP, 14x20mm ThermallyEnhanced Package Applications * Drive-Side Deskew in High-Speed Memory Testers * Direct RAMBUS DRAM, SLDRAM, DDR SDRAM, Fast SSRAM * High-Speed Instrumentation: Pulse Generators, Timing Margin Testers for Datalink, Interface, and Disk Drive Applications * Telecom, Datacom, and Computer Deskew General Description The VSC6250 is intended for use in the next generation of high-speed, high-accuracy memory testers for devices such as Direct RAMBUS DRAM, SLDRAM, DDR SDRAM, and fast SSRAM. The VSC6250 provides ultra-precise timing to allow next generation memory testers to achieve excellent overall timing accuracy. Timing delays of the VSC6250 are extremely stable with respect to temperature and voltage. Proprietary circuit design and process technology reduce pattern, data, frequency, and duty-cycle dependencies to an absolute minimum. The VSC6250 requires no external DACs, which eliminates errors due to DAC reference noise and analog crosstalk, and DAC temperature and voltage drift. The VSC6250 is available in a 128-pin PQFP, 14x20mm thermally-enhanced package. G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC Data Sheet VSC6250 VSC6250 Block Diagram S R Output 0 DINA S R Output 7 DIN S R Output 8 DINB S R Output 15 Reference Clock (250MHz) Stability Control Parallel Data Interface Page 2 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52197-0, Rev. 4.0 8/19/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 Functional Description 1Gb/s 16-Channel Drive-Side Deskew IC The VSC6250 is a 1Gb/s 16-channel drive-path deskew IC designed for deskewing differences in path delay between multiple DUTs in a high-speed memory test system. The VSC6250 can be used as two independent 1:8 fanout and deskew sections or as a single 1:16 fanout and deskew. When used as two 1:8 deskews, input signals are applied to inputs DINA and DINB. When used as a single 1:16 deskew, the input is applied to input DIN. The VSC6250 is designed to operate with a conventional 500MHz timing generator which outputs formatted pulses to the VSC6250 deskew IC. See Figure 1. The waveform at the input of the VSC6250 is the same as that presented to the DUT pin. In a memory tester, such a 500MHz timing generator IC may be designed: * Using one edge to output a single 500Mb/s data stream * Using two edges to output a single 500Mb/s data stream preceded its complement * Using three edges to output a single data stream at 500Mb/s surrounded by its complement * Using two edges to output two interleaved 500Mb/s data streams for an aggregate bandwidth of 1Gb/s. Formatting is performed inside the timing generator IC. An example interface between the timing generator IC and the deskew is shown in Figure 1. This configuration is capable of supporting the four different data output choices, with appropriate design of the formatting logic. The VSC6250 can handle pulses with a data rate up to 1Gb/s or a pulse repetition rate up to 2ns. A timing diagram for the VSC6250 is shown in Figure 2. Figure 1: VSC6250 Interface to Timing Generator IC Timing Generator VSC6250 Timeset/Dataset RAM S R Format Logic S R S R Figure 2: VSC6250 AC Timing Diagram tREFIRE DINx tPWO DOUTx tPDR tPDF tPWI G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC Data Sheet VSC6250 The delay of each of the deskewed outputs can be adjusted separately to compensate for differences in path length between DUTs on a single test head. The maximum delay is 7ns. Delay span is 5ns. Usable range is a minimum of 4ns(1). Resolution is 8ps. To compensate for pulse dispersion in pin electronics, delay of the rising and falling edges can be adjusted independently. To ensure timing performance, delay of the VSC6250 is measured in production at every time step of every vernier. Figure 3 shows measured output waveforms of the VSC6250. Figure 3 (a) shows a measured minimum output pulse width. The specified mimimum output pulse width is 500ps, but this measurement shows operation down to 300ps. Figure 3 (b) shows typical timing resolution of 8ps. Figure 3: VSC6250 Measured Output Waveforms a) Mininum output pulse width of 300ps (b) Typical timing resolution of 8ps With next generation testers required to test more DUTs per testhead in the same footprint, board area is a critical design parameter. Providing 16 deskew channels in a 14mmx20mm thermally-enhanced 128-pin PQFP package, the VSC6250 consumes less than 1/2 the total board area of the bipolar alternative. Page 4 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52197-0, Rev. 4.0 8/19/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 1Gb/s 16-Channel Drive-Side Deskew IC The 32 delays (rising and falling edges for 16 channels) in the VSC6250 are programmed using a parallel interface. Verniers are selected by a 5-bit address word and controlled by two function enable bits. Each vernier requires 11 bits to set the delay value. Power dissipation of the VSC6250 is less than 5W from a single -2V supply. Table 1: Operational Mode Truth Table Mode # 1 2 Mode Name Cal Mode User Mode CALENN 0 1 Mode Description Sets timing delays with each vernier selected with ADR [3:0] Serial Data Input. Generates timing delays as set by data in Cal Mode. Figure 4: CAL Mode Timing Diagram ADR[4:0] CALENN D[10:0] MSB LSB Don't Care 10 9 Load Calibration Register Data Latch Transparent Latch Data into Data Latch Measure Delay 1 CAL Cycle G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC Figure 5: CAL Mode: Pre-Calibration Delay Range Data Sheet VSC6250 32 Coarse Vernier Steps + 64 Fine Vernier Steps(1) Delay ~275ps Fine Vernier Range 000 Delay[0:10] Figure 6: CAL Mode: Post-Calibration Delay Range 32 Coarse Vernier Steps + 64 Fine Vernier Steps(1) Delay = Unused Codes 000 Delay[0:10] NOTE: (1) There are 32 coarse vernier codes and 64 fine vernier codes. Not all of the codes are used to reach maximum delay. The current design utilizes 22 coarse codes and 47 fine vernier codes. Future designs will utilize 22 course designs and 59 fine vernier codes. These numbers must be used when calculating INL and DNL. System calibration should be performed with the maximum usable codes. When a code is programmed beyond the maximum utilized code, the delay will toggle between maximum delay and maximum delay minus 1LSB. Please contact your local Vitesse sales representative to determine when the future design will be available. Page 6 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52197-0, Rev. 4.0 8/19/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 AC Timing Characteristics Table 2: AC Timing Characteristics Parameter tPDR(MIN), tPDF(MIN) tPDR(MAX), tPDF(MAX) tPD(SPAN) tRES DNL tPWI tPWO FRCK DTDD DTDT PSRR tR/tF tREFIRE JO 1Gb/s 16-Channel Drive-Side Deskew IC Description Propagation Delay, Minimum Delay Propagation Delay, Maximum Delay Propagation Delay, Span Delay Element Resolution Delay Differential Nonlinearity Input Pulse Width Output Pulse Width Reference Clock Frequency Variation in Delay vs. Duty Cycle Variation in Delay vs Temperature Power Supply Rejection Ratio(1) Output Rise Fall Times (20% to 80%) Adjacent Edge Spacing Output Jitter Min 4.1 9.9 5.8 -- -2 0.75 0.5 -50 -- -- -- 2 -- Typ 5 11.6 -- 8 -- -- -- 250 -- 2 -- 300 -- 3 Max 6.5 13.5 7 20 +2 -- -- -- +50 -- 230 -- -- -- Units ns ns ns ps LSB ns ns MHz ps ps/C ps/100mV ps ns ps rms NOTE: (1) Change in range of maximum delay. . Figure 7: AC Timing Diagram DINx tPDF(MAX) tPDF(MIN) tPDR(MAX) tPDR(MIN) DOUTx tPDR(SPAN) tPWO tPDF(SPAN) G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC Data Sheet VSC6250 DC Characteristics Table 3: Single Ended ECL Inputs and Outputs Parameter VOH VOL VIH VIL IIH IIL Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min -1020 -2000 -1165 -2000 -50 Typ -- -- -- -- -- -- Max -700 -1620 -700 -1475 200 -- Units mV mV mV mV A A Conditions VIN = VIH (max) VIN = VIL (min) NOTE: VTT = -2.0V 5%, VCC = VCCA = GND, RLOAD = 50 to -2.0V, external reference (VREF) = -1.32V 25mV. Table 4: Differential ECL Inputs and Outputs Parameter VINDIFF Description Input Voltage Differential Min 200 Typ -- Max -- Units mV Conditions Required for full output swing Common-mode range required for full output swing with VDIFF applied Output voltage swing Common-mode output voltage VINCM VOUTDIFF VOUTCM Input Common-Mode Voltage -1.5 -- -0.5 V Output Voltage Differential Output Common-Mode Voltage 400 -1.5 -- -- -- -0.7 mV V Table 5: VSC6250 Power Dissipation Parameter ITT PD Description VTT Supply Current Power Dissipation (1) Min -- -- Typ 2000 4 Max 2870 6 Units mA W Conditions NOTE: (1) Output power dissipation does not include load power. Page 8 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52197-0, Rev. 4.0 8/19/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 Absolute Maximum Ratings(1) 1Gb/s 16-Channel Drive-Side Deskew IC Power Supply Voltage (VTT) ...........................................................................................................-2.5V to +0.5V ECL Input Voltage Applied, (VIN ECL)................................................................................. +0.5V to VTT + -0.5V Output Current (IOUT) .................................................................................................................................... 50mA Case Temperature Under Bias (TC) ............................................................................................. -55oC to + 125oC Storage Temperature (TSTG)......................................................................................................... -65oC to + 150oC Recommended Operating Conditions Power Supply Voltage (VTT)................................................................................................................. -2.0V 5% Commercial Operating Temperature Range(2) (T) ............................................................................ 30oC to 70oC NOTES: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) Lower limit of specification is ambient temperature and upper limit is case temperature. ESD Ratings Proper ESD procedures should be used when handling this product. The VSC6250 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC Data Sheet VSC6250 Figure 8: Pin Diagram VDD VTT CHPRST VDD ASYNCRST VTT VTT DATA10 DATA9 VDD DATA8 DATA7 DATA6 DATA5 VTT VTT VDD VDD VDD DATA4 DATA3 DATA2 VTT DATA1 DATA0 VDD Package Information VTT VDD DOUT7 DOUT7N VDD DOUT6 DOUT6N VTT DOUT5 DOUT5N VDD DOUT4 DOUT4N VDD RCK RCKN VDD VTT VTT VTT DOUT3 DOUT3N VDD DOUT2 DOUT2N VDD DOUT1 DOUT1N VDD DOUT0 DOUT0N VTT VTT VTT VDD ADR4 ADR3 VDD 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 CALENN VREF VTT NC NC VDD VTT VDD VTT VDD DOUT8N DOUT8 VTT DOUT9N DOUT9 VDD DOUT10N DOUT10 VTT DOUT11N DOUT11 VDD DOUT12N DOUT12 VTT DOUT13N DOUT13 VDD DOUT14N DOUT14 VTT DOUT15N DOUT15 VDD NC VDD VTT VTT Page 10 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 ADR2 ADR1 VTT ADR0 VTT VTT DINAN DINA DINN DIN VDD DINBN DINB VDD VDD ECLHI NC VTT VTT VTT VDD VTT VTT VTT NC NC 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VITESSE VSC6250 G52197-0, Rev. 4.0 8/19/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 Table 6: Pin Identifications Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1Gb/s 16-Channel Drive-Side Deskew IC Signal Name VTT VDD DOUT7 DOUT7N VDD DOUT6 DOUT6N VTT DOUT5 DOUT5N VDD DOUT4 DOUT4N VDD RCK RCKN VDD VTT VTT VTT DOUT3 DOUT3N VDD DOUT2 DOUT2N VDD DOUT1 DOUT1N VDD DOUT0 DOUT0N VTT VTT VTT VDD ADR4 ADR3 Signal Type -- -- O O -- O O -- O O -- O O -- I I -- -- -- -- O O -- O O -- O O -- O O -- -- -- -- I I Levels -2.0V 0V ECL ECL 0V ECL ECL -2.0V ECL ECL 0V ECL ECL 0V ECL ECL 0V -2.0V -2.0V -2.0V ECL ECL 0V ECL ECL 0V ECL ECL 0V ECL ECL -2.0V -2.0V -2.0V 0V ECL ECL Description Power Supply Ground Output Channel 7, True Output Channel 7, Complementary Ground Output Channel 6, True Output Channel 6, Complementary Power Supply Output Channel 5, True Output Channel 5, Complementary Power Supply Output Channel 4, True Output Channel 4, Complementary Ground 250 MHz Reference Clock, True 250 MHz Reference Clock, Complementary Ground Power Supply Power Supply Power Supply Output Channel 3, True Output Channel 3, Complementary Ground Output Channel 2, True Output Channel 2, Complementary Ground Output Channel 1, True Output Channel 1, Complementary Ground Output Channel 0, True Output Channel 0, Complementary Power Supply Power Supply Power Supply Ground Address Bit 4 for Vernier Selection Address Bit 3 for Vernier Selection G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC Pin # 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Data Sheet VSC6250 Signal Type -- I I -- I -- -- I I I I -- I I -- -- O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O -- O O -- Signal Name VDD ADR2 ADR1 VTT ADR0 VTT VTT DINAN DINA DINN DIN VDD DINBN DINB VDD VDD ECLHI NC VTT VTT VTT VDD VTT VTT VTT NC NC VTT VTT VDD NC VDD DOUT15 DOUT15N VTT DOUT14 DOUT14N VDD Levels 0V ECL ECL -2.0V ECL -2.0V -2.0V ECL ECL ECL ECL 0V ECL ECL 0V 0V ECL -- -2.0V -2.0V -2.0V 0V -2.0V -2.0V -2.0V 0V 0V -2.0V -2.0V 0V 0V 0V ECL ECL -2.0V ECL ECL 0V Description Ground Address Bit 2 for Vernier Selection Address Bit 1 for Vernier Selection Power Supply Address Bit 3 for Vernier Selection Power Supply Power Supply Input A, Complementary Input A, True Common Input, Complementary Common Input, True Ground Input B, Complementary Input B, True Ground Ground ECL High Voltage Not Connected Power Supply Power Supply Power Supply Ground Power Supply Power Supply Power Supply Not Connected Not Connected Power Supply Power Supply Ground Not Connected Ground Output Channel 15, True Output Channel 15, Complementary Power Supply Output Channel 14, True Output Channel 14, Complementary Ground Page 12 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52197-0, Rev. 4.0 8/19/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 Pin # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 1Gb/s 16-Channel Drive-Side Deskew IC Signal Name DOUT13 DOUT13N VTT DOUT12 DOUT12N VDD DOUT11 DOUT11N VTT DOUT10 DOUT10N VDD DOUT9 DOUT9N VTT DOUT8 DOUT8N VDD VTT VDD VTT VDD NC NC VTT VREF CALENN VDD DATA0 DATA1 VTT DATA2 DATA3 DATA4 VDD VDD VDD VTT VTT Signal Type O O -- O O -- O O -- O O -- O O -- O O -- -- -- -- -- -- -- -- DC I -- I I -- I I I -- -- -- -- -- Levels ECL ECL -2.0V ECL ECL 0V ECL ECL -2.0V ECL ECL 0V ECL ECL -2.0V ECL ECL 0V -2.0V 0V -2.0V 0V -- -- -2.0V -1.32V ECL 0V ECL ECL 0V ECL ECL ECL 0V 0V 0V -2.0V -2.0V Description Output Channel 13, True Output Channel 13, Complementary Power Supply Output Channel 12, True Output Channel 12, Complementary Ground Output Channel 11, True Output Channel 11, Complementary Power Supply Output Channel 10, True Output Channel 10, Complementary Ground Output Channel 9, True Output Channel 9, Complementary Power Supply Output Channel 8, True Output Channel 8, Complementary Ground Power Supply Ground Power Supply Ground Not Connected Not Connected Power Supply ECL Reference Voltage Write Delay Register Ground Delay Bit 0 Delay Bit 1 Power Supply Delay Bit 2 Delay Bit 3 Delay Bit 4 Ground Ground Ground Power Supply Power Supply G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC Pin # 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Data Sheet VSC6250 Signal Type I I I I -- I I -- -- I -- I -- -- Signal Name DATA5 DATA6 DATA7 DATA8 VDD DATA9 DATA10 VTT VTT ASYNCRST VDD CHPRST VTT VDD Levels ECL ECL ECL ECL 0V ECL ECL -2.0V -2.0V ECL 0V ECL -2.0V 0V Description Delay Bit 5 Delay Bit 6 Delay Bit 7 Delay Bit 8 Ground Delay Bit 9 Delay Bit 10 Power Supply Power Supply Asynchronously resets all vernier outputs to logic LOW. Ground Chip Reset. Resets all vernier outputs to LOW and initializes all delay registers to zero. Power Supply Ground Page 14 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52197-0, Rev. 4.0 8/19/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 Package Information 128-Pin Thermally-Enhanced PQFP 1Gb/s 16-Channel Drive-Side Deskew IC Body + 3.2mm Footprint, 2.70mm Thick DIMENSIONS A A1 A2 D D1 E E1 L e b 1 ddd ccc LEADS 3.40 0.25 / 0.50 2.70 17.20 14.00 23.20 20.00 0.88 0.50 0.22 0 - 7 6 0.8 MAX. 0.08 TOLERANCES MAX. MIN./MAX. 0.10 0.20 0.10 0.20 0.10 +0.15 / -0.10 BASIC 0.05 4 MAX. NOTES: 1) All dimensions in mm. 2) Dimensions shown are nominal with tolerances as indicated. 3) Foot length "L" is measure at gage plane, 0.25 above the seating plane. G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC Data Sheet VSC6250 Package Thermal Characteristics The VSC6250 is packaged in an 128-pin, 14x20mm thermally-enhanced PQFP with an internal heat spreader. These packages use industry-standard EIAJ footprints, which have been enhanced to improve thermal dissipation. The construction of the packages are as shown in Figure 9. The VSC6250 is designed to operate with a case temperature up to 90oC. The user must guarantee that the temperature specification is not violated. Figure 9: Package Cross Section Exposed Heat Slug Insulator Plastic Molding Compound Lead Wire Bond Thermal Epoxy Die Table 7: Thermal Resistance Symbol JC CA-0 CA-100 CA-200 CA-400 CA-600 CA-800 Description Thermal resistance from junction-to-case Thermal resistance from case-to-ambient, still air Thermal resistance from case-to-ambient, 100 LFPM air Thermal resistance from case-to-ambient, 200 LFPM air Thermal resistance from case-to-ambient, 400 LFPM air Thermal resistance from case-to-ambient, 600 LFPM air Thermal resistance from case-to-ambient, 800 LFPM air Value 6.6 23 21 19.9 18 17.3 16.6 Units o o o o o o o C/W C/W C/W C/W C/W C/W C/W Page 16 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52197-0, Rev. 4.0 8/19/00 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC6250 Ordering Information 1Gb/s 16-Channel Drive-Side Deskew IC The part number for this product is formed by a combination of the device type and the package style: VSC6250 Device Type 1Gb/s 16-Channel Drive-Side Deskew IC xx Package QW: 128-Pin, 14x20mm Body Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products, specifications, or other information at any time without prior notice. Therefore the reader is cautioned to confirm that this data sheet is current prior to placing any orders. The Company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation's products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited. G52197-0, Rev. 4.0 8/19/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION 1Gb/s 16-Channel Drive-Side Deskew IC This page left intentionally blank. Data Sheet VSC6250 Page 18 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52197-0, Rev. 4.0 8/19/00 |
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